As is well known, electrically programmable non-volatile memories are structured in cell matrix each of which comprises an MOS transistor with floating gate and relative areas of drain and source.
The programming of a memory cell is strongly influenced by a vd voltage applied to its drain terminal. In particular, for the non-volatile FLASH type memory cells, a reduced degree of vd drain voltage means a slow and insufficient programming of the cell, whilst an excessive degree of voltage leads to a partial erasing of the cell (so-called `soft-erasing phenomenon`).
The preceding considerations bring us to the conclusion that it is necessary to provide the circuit comprising the Flash memory with a voltage regulator which is particularly refined and precise in providing the correct drain voltage to the cells to be programmed.
A first technical solution known to satisfy this requirement consists of the so-called differential adjustment, illustrated in FIG. 1 for an M1 non-volatile single feed voltage memory cell.
In particular, the memory cell M1 is inserted between a ground voltage reference GND and a programming voltage reference Vpd. This programming voltage reference Vpd is suitably derived from a boosted voltage Vpump obtained by means of a booster circuit 1, for example of the load pump type.
The drain terminal D1 of the memory cell M1 is connected to the programming voltage reference Vpd via the series of a program selection block, or program load 2, and a column decoder 3. The program load block 2 consists conventionally of a logical inverter IL1 and a transistor M2, in particular of the PMOS type. In practice, the program load block 2 represents a family of `on` switches for the column decoder 3.
The column decoder 3 consists of a chain of decoding transistors, having control terminals YO, YN, YM which are connected to a first reference voltage for the decoding of the Vpcy column.
The drain voltage Vd of the memory cell M1 is therefore given by the difference between the programming voltage Vpd and a .DELTA.V.sub.c equal to a drop in voltage due to the chain of decoding transistors YO, YN, YM, of the decoder 3, as well as serial resistors of the `bit line`, r.sub.d, and of the source terminal, r.sub.s : EQU Vd=Vpd-.DELTA.V.sub.c (1)
In order to limit such a drop in .DELTA.V.sub.c voltage the Vpcy column decoder voltage to be applied to the terminal decoding ports of the transistor chain YO, YN, YM of the decoder 3 must be raised, in order to keep them in the so-called `triode` operating zone.
The control terminal G1 of the memory cell M1 is in the same view connected to the second Vpcx row decoder voltage reference.
The programming voltage reference Vpd is on an output terminal OUT of a differential regulator 4.
Such differential regulator 4, comprising a differential stage 5 controlled by the boosted voltage Vpump generated by the booster circuit 1, is for limiting the current which flows in the M1 memory cell during the programming phase by stabilizing programming voltage Vpd.
Such differential stage 5 has an inverting input terminal 7, connected to a bandgap circuit 6, a non-inverting input terminal 8, connected to a ground reference GND by means of an initial R1 resistive element, and an output terminal 9, connected to the output terminal OUT of the differential regulator 4, as well as a feedback connection to a feed terminal 10 by means of a connecting transistor M3.
Such feed terminal 10 of the differential stage 5 is also connected to a booster circuit 1 which supplies the boosted voltage Vpump.
Furthermore, the output terminal OUT of the differential regulator 4 is connected to the ground reference GND by means of a filtering and compensation capacitance Cf as well as to the non-inverting input terminal 8 of the differential stage 5, by means of a second resistive element R2.
Thanks to the above mentioned differential regulator 4, the programming voltage Vpd for the drain terminal D1 of the memory cell M1 is obtained from a voltage control V.sub.BG supplied by a bandgap circuit 6 at the inverting input terminal 7 of the differential stage 5.
In particular, the connecting transistor M3 is a PMOS type pass transistor, controlled by the differential stage 5, in order to produce a voltage transfer between the boosted voltage Vpump and the programming voltage Vpd. Such pass transistor M3 puts the load pump booster in communication with the bit-line comprising the memory cell M1, therefore making full use of the boosted voltage Vpump.
In fact, when its control terminal receives the boosted voltage Vpump, the connecting transistor M3 is off and takes the programming voltage Vpd present on the output terminal OUT of the differential regulator 4 to ground GND. In parallel, when the control terminal thereof is subjected to a ground voltage GND, the connecting transistor M3 is operating in the ohmic zone and transfers the entire boosted voltage Vpump onto the output terminal OUT of the differential regulator 4.
In other words, the connecting transistor M3 switches the booster circuit 1 connection on and off at the charge pump with the bit-line of the memory cell M1.
Finally, the presence of the filtering and compensation capacitance Cf, in correspondence to the output terminal OUT of the differential regulator 4, carries out a compensation of the structure in its whole, allowing at the same time for a load storage which is useful in the first stages of the programming of the cell M1.
Such filtering and compensation capacitance Cf is conveniently of the value of some tens of picofarads. In mathematical terms, it introduces a pole in the transfer function of the differential regulator 4.
It is useful to note that the filtering and compensation capacitance Cf could not be substituted, for the scope of compensation, via a Miller capacitance placed between terminals 9 and OUT, since the difference of potential between these terminals can undergo inversions according to the conditions of the operating of the device.
The differential regulator 4 also has drawbacks, of which the most important is in that it makes use of a PMOS transistor as a connecting transistor M3.
In fact this PMOS transistor must be configured at a common source terminal (common source configuration), in this way making the loop gain of the structure comprising the differential regulator 4, the program load 2 and the column decoder 3 dependent on the number of cells programmed and increase accordingly, in consequence, the value of this gain.
More precisely, the loop gain of the structure is therefore given in the following formula: EQU G.sub.LOOP =A.sub.0 (S)*g.sub.m(PMOS) *R1/(1+SCf(R1+R2)) (2)
wherein: A.sub.0 (S) is the gain of the differential stage 5;
g.sub.m(PMOS) is the transconductance of the PMOS type connecting transistor M3. PA1 an inverting input terminal connected to an earth ground reference; PA1 a feed terminal connected to a positive voltage booster circuit which delivers a boosted voltage; and PA1 an output terminal connected to an output terminal of the voltage regulator, in order to produce an output reference voltage from the comparison of input voltage; the voltage regulator further comprising: PA1 Another embodiment of the invention is directed to a programming structure for the drain voltage of a single feed memory cell, comprising at least one voltage regulator according to the invention, with an output terminal connected to the drain terminal of the memory cell by means of a series of program selection block, and column decoder, in such a way as to self-limit the charge current of the drain terminals of the cells to which this voltage regulator is connected.
The loop gain G.sub.LOOP of the structure, represented by the above mentioned formula (2) depends disadvantageously on the number of programmed cells controlled by the differential stage 5. In fact, the g.sub.m(PMOS) transconductance of the connecting transistor M3 increases as the current absorbed at the output terminal OUT of the differential regulator 4 increases, this current depending on the number of cells programmed (i.e., the number of cells where current flows through). The increase of the g.sub.m(PMOS) transconductance causes an increase in the loop G.sub.LOOP gain when the differential regulator 4 is stimulated, that is to say when the memory cells connected thereto absorb current. In particular, the phase margin of this loop gain G.sub.LOOP is dangerously reduced.
In a simulation carried out by the applicants themselves, it was possible to note an increase in the loop G.sub.LOOP gain at zero frequency from a value of 32 (with an unloaded regulator) to a value of 250, in the particular case of eight programmed cells connected to the differential regulator 4.
The filtering and compensation capacitance Cf introduces a dominant pole into the loop G.sub.LOOP gain structure.
Because of the dependence of this gain from the number of programmed cells controlled by the differential 5 stage, this capacitance must therefore be oversized based on the critical case, in order to guarantee structure stability in all operative conditions, even in the presence of significant increases of the g.sub.m(PMOS) transconductance.
All this means a penalizing increase in the silicon area required for the integration of the structure in its whole.
Furthermore, in the programming phase, when the program loads 2 are enabled a higher flux of current starts to flow towards the drain terminals of the programmed memory cells to be programmed. In this case, the programming voltage Vpd undergoes a dramatic drop: the differential stage 5 can come out of its linear dynamics and lose its connection with the programmed voltage Vpd.
The PMOS connecting transistor M3 continues to conduct, but without being able to control the current flowing towards the programming memory cells to be programmed, also because of its configuration at common source.
The output terminal OUT, on which the programming voltage Vpd is present, is therefore recharged by the differential stage 5 without any control by the introduced reaction, in normal circumstances.
This situation remains until the differential 5 stage returns to linear dynamics.
All this can cause undesired spikes or surges in the drain voltage of the memory cells to be programmed, as schematically shown in FIG. 2. In particular, FIG. 2 shows the results of a simulation carried out by the applicants themselves, in the case of the programming of 4 memory cells using respectively filtering and compensation capacitance Cf of 50 and 100 pF. This easily shows that with filtering and compensation capacitance Cf of higher values the spike or surge in the drain voltage of the programmed cells to be programmed is damped.
The only solution to obviate this dangerous situation is therefore by employing the filtering and compensation capacitance Cf with an extremely high value, with above disclosed disadvantageous consequences in terms of occupation of the areas of integration.
More precisely, since the slew-rate of the structure in its whole is proportional to the gain*band product, in order to slow down the upward transitory of the programmed voltage Vpd, in the unhooking conditions of the feedback introduced at the differential stage 5, it is necessary to increase the value of the filtering and compensation capacitance Cf to 100 pF, with an increase of occupied silicon area which is absolutely infeasible.